Simultaneous carry adder



DSC 27, 1960 G. B. RosENBERGER 2,966,305

SIMULTANEOUS cARBy ADDER 8 Sheets-Sheet 1 Filed Aug. 16, 195'? Dec. 27,1960 G. B. RosENBERGER sIMuLTANEous CARRY ADDER 8 Sheets-Sheet 2 FiledAug. 16, 1957 DeC- 27, 1960 G. B. RosENBl-:RGER 2,966,305

smuLTANEous CARRY ADDER 8 Sheets-Shale?. 25

Filed Aug. 16, 1957 DeC- 27, 1950 G. B. RosENBI-:RGER 2,966,305

SIMULTANEoUs CARRY ADDER 8 Sheets-Sheet 4 Filed Aug. 16, 1957 I I I I IA I I I I I I CI" l BITI SLilm f(xI ,y0

EDEL. I

BIT 2 Sum 2 fIx2,y2I gDEL BIT 3 Sum f(x3,y3)

BIT 4 Stm f(x4,y4) DEL BIT 5 Sum fIX5,y5I 2DEL BIT 7 Sum 7 EDEL BIT 8Sum fIX8,y8I aDEL BIT 9 Sum f(x9,y9)

FIG. 2

CIm-

OCTAL CARRY =I=I= I CIN I- I I I I OUT Dec. 2 7, 1960 G. B. ROSENBERGERSIMULTANE'OUS CARRY ADDER Filed Aug. 1e,` 1957 8 Sheets-Sheet 5 IG'G x YOUTPUT UP UP DOWN *JY UP ,DOWN UP Y DOWN UP UP DOWN DOWN UP x Y z OUTPUTZ UP UP UP DOWN l DOWN UP UP DOWN X UP DOWN UP DOWN O A -1 +Y1z DOWNDOWN UP UP Y UP UP DOWN UP DOWN DOWN DOWN UP DOWN UP DOWN UP UP DOWNDOWN UP 1 1NPUT OUTPUT A I ,B=A UP DOWN DOWN UP FIG 3 TRUTH TABLE xn 1 1O O 1 1 O O Yn 1 O 1 O 1 O 1 Ov C111 cn-1O O O O 1 1 1 1 )in s1v O 1 1 O1 O O 1 n 'so 1 O O 1 O 1 1 O Cn 1 O O O 1 1 1 O Dec. 27, 1960 G. B.RosENBl-:RGER

sIMULTANEoUs CARRY ADDER 8 Sheets-Sheet 6 Filed Aug. 16, 1957 FIG. 7

ADDITIONAL |NPUTS 47ypf D= ABC 253i l v P /250 236 I 47PPf T' -iOV 8Sheets-Sheet 7 Filed Aug. 16, 1957 Ele. 9

ADDITIONAL INPUTS 6 P D| VMI; w J V .T F K f 3 mr w/ 3 K m 2. ,W Jl? 2 86 f 7 D 4 2/ DI N P Dl N DI w w H K O m h Wl 2 K WM @u .n 4 u, m n d wINTA? T w K f u w, m B

Dec. 27, 1960 G. B. ROSEN BERGER SIMULTANEOUS CARRY ADDER Filed Aug. 16,1957 FIG. i0

8 sheets-sheet s United States Patent O SIMULTANEOUS CARRY ADDER GeraldB. Rosenberger, Wappingers Falls, N.Y., assigner to InternationalBusiness Machines Corporation, New York, N.Y., a corporation of New York4Filed Aug. 16, 1957,Ser. No. 678,573

'8 Claims. (Cl. 23S-175) This invention `relates to adders and moreparticularly to an adder for the parallel addition of binary numbers inwhich the serial carry operation arising in such parallel addition isbroken up into groups for serial carry operation by such groups, carriesbetween groups being generated simultaneously with the addition of thenumbers.

Many large scale binary computers must allow Vfor maximum full carrytime in each addition since it is possible for a carry generated in the-iirst position to ripple through the highest order position of theadder. An illustration of such a case would be in the addition of thedecimal number 7 expressed in binary form as "Olll and the decimalnumber 1 expressed in binary form as 0001. From the addition of 'thesetwo numbers it will be noted that the carry is propagated from thelowest order position and is rippled from order to order to the fourthorder position in the binary 'sum 1000. The propagation of the carrytakes time and the resulting delay is accumulative. Accordingly, thetime alloted for the ;car,ry process must be alloted on the basis of theworst vcase which would be the time it takes a carry to ripple throughall of the orders of rthe adder although the average carry sequences areshorter in time than the maximum. Since a need has been shown for 'highcomputation speeds, at least some speed up should be expected to comefrom the decrease in operation time of 'basic arithmetic apparatus. Theripple carry process is one such Aoperation in which Vsignicantdecreases in time may be made .since the resolution of .the sum in anybit of the adder may have to wait for carry signal to propagate throughall lower order bits.

lt will be shown hereafter that the carry intoany adder Abit may beexpressed as a function of the original carry in and all lower order bitpositions ofthe adder. `Utilization of this principle at -the twoextremes is mentioned briefly so that it will Aclarify the basic 'schemeas well Yas emphasize the problems involved. One extreme is 'to ripplethe carry two bits at a time which means the original carry into oneposition will be used to form a C arry into the third bit while it wasperforming its function in bits l and 2. A carry into the third bitvwould be used to generate the carry in Vfor the fth -bit while it wasperforming its function in bits 3 yand 4. The `other extreme is to formthe carry into each adder bit immediately, this means having anindependent carry'generation in the circuit for each adder bit. Thecomplexity of these circuits increases approximately factorial with theincrease in the order above. Neither of the two 4extremes seems to odermuch promise because in one instance operation is too slow, and in theother instance circuit complexity and cost are excessive.

One object of this invention is to iind the best compromise betweenspeed and circuit complexity. vMany schemes are possible including thedevelopment of one carry for every four bits =an`d another forgenerating one carry for every six bits, butrsincethese are very similarto the octal scheme and because they do vnot :afford all of theadvantages that the nine bit scheme does, lthey have assumed secondaryimportance to the nine vbit schemes. The preferred embodiment of thisinvention is directed to the nine bit octal scheme wherein vthe nine bitadder is divided into groups of three bits and the carry is rippledthrough bits 1, 2 and 3 simultaneously with the carry rippling throughbits 4, 5 and 6 and through bits 7, 8 and 9. The carries into bitpositions 4, 7 and 1() are generated coincidentally with the addition ofthe 'bits 'in the manner to be described later. The present inventionprovides an adder which develops a carry input to the highest orderstage long before all of the sums of the lower order bits have beenresolved.

lt is an object of this invention to provide an improved adder in whichthe speed of operation is increased by employing Asimultaneous carrywith the orders in groups to increase carry propagation speed.

It is another object of this invention to provide an adder for formingthe sum of binary numbers comprising an adder order for each binaryposition, each effective to form the sum Vof at least two numbers at anoutput and for generating a carry at another output, circuit connections for each lower adder order carry to each higher order adder, andtransistor logical circuits responsive to the carry status of each adderorder and the carry in, if any, into the lowest adder order forgenerating a carry signal as an output of the adder in coincidence withthe addition of the binary numbers.

It is a still further object of this invention to provide an improvedsolid state parallel adder in which the serial carry operation `isdivided :into groups for Serial carry propagation by such groups andcarries between groups are generated simultaneously with the addition ofthe numbers,

It is another object of this invention to provide an improved adderorder for Aforming the sum of two binary numbers.

It is another object of this invention to provide an irnproved fulladder using solid state circuit elements..

It is another object of this invention to provide logical -circuits .forforming lthe carry out of a group of adders ,simultaneously with thelforming of thesumof thefbinary finput.

It is another object of this invention to `provide a carry ,generationcircuit for a group of adder ,orders comprising negative logic circuits.

It is a still further object of this invention to provide a chain ofcarry generation circuits, one for each group of adder orders, in whicheach successive carry generation circuit derives signals representing"the carry status of the lower order adder groups to provide carrysignalsbetween adder groups.

It is another object o'f this invention to provide an ,adder comprisingthree groupsof three adder ordersand three carry generation circuits,the first of the carry generation circuits providing a carry into thefourth ,Order which is a .function of X1, Y1, X2, Y2, X3, Y3 and Cm, asecond of the carry generation circuits providing a Acarry into theseventh order of the adder which is a function 0f X1, Y1, X2, Y2, X3,Ya, X4, Y4, X5, Yr Xs, Ys and Cin, and the lthird carrygenerationcircuit Nproviding Ya Ycarry out of the ninth adder order which is afunction of the binary inputs to all of the adder orders and the carryin signal.

Other objects of the invention will be pointed ,out in the followingdescription and claims and illustrated in the accompanying drawingswhich disclose by way of example the principle of the invention and thebest mode which has been contemplated of applying that principle.

In the drawings:

Figures la, lb and lc, placed one above the other, in

`that order, form the logical block diagrams for nine bits (AND) circuitand the truth table for such a circuit.

Figure 7 is the transistor diagram of an AND circuit which isillustrated in block form in Figure 6.

Figure 8 is a block diagram of an OR AND NOT (OR AND) circuit and thetruth table for the various combinations of inputs with the resultingoutputs.

Figure 9 is a circuit diagram for OR AND circuit which is illustrated inblock form in Figure 8.

Figure l is the logical block diagram for the generation of the carryout of a single position of the adder.

Figure 11 is a logical block diagram of the generation of the sum in asingle position of the adder.

Figure 12 is an illustration of the positive logical blocks required toperform the negative logic of Figure 4.

The logical block diagram of Figures la, 1b and 1c illustrate the mannerin which the principles of the invention shown functionally is performedin Figure 2.

With reference to the adder of Figure 3 and its associated truth table,it can be shown that Since C=C(out) and Cn 1=C(in), the generalexpression for the carry out of a stage is a function of the carry in.

The expression for the carry out of the N stage will be derived from thetruth table and used to develop a simultaneous carry expression-that is,to show how any carry can be expressed as a function of the carry intothe lowest order bit without waiting for the carry to ripple through allthe lower order bits.

Now, if Cn=xyn-|-Cn 1(xniyn), the carry out of the lowest order bit, C1is:

Substituting C1 in the expression for C2 C2=X2y2+x1y1(x2+y2) -l-(x14-y1) (x2-Pye) Cin and As shown by the derivation and as illustratedin Figure 2, the carry into the fourth position is a function of x1, y1,x2, y2, x3, y3, and the carry in (Cm). More specifically, the carry intothe fourth position (C3) is equal to D3 or D2 and P3 or D1 and P2 and P3or P1 and P3 and P3 and Cin. The carry into the seventh position is afunction of x1, y1, x2, y2, x3. ya, x4, yi, x5, ya xs, ya, and carryinto the first position (Cin).

Accordingly, the carry into the seventh position can be expressed as D5or D5 and P5 or D4 and P5 and P5, or D3 and P5 and P5 and P4 or D2 andP5 and P5 and P4 and P3 or D1 and P5 and P5 and P4 and P3 and P2 or P5and P5 and P4 and P3 and P3 and P1 and Cm. Similarly, the carry into thetenth position is the function of xr, Y1, X2, y2 xs, ya, x4, yo x5 ys,Xs, Y6, x1, )"1, xs, ya, X9, ya and carry into the first position.Accordingly, this expression is C555 equals D5 or D3 and P9 or D7 and P3and P5 or D5 and P7 and P3 and P9 or D5 and P5 and P7 and P3 and P9 orD4 and P5 and P6 and P7 and P5 and P3 or D3 and P4 and P5 and P5 and P7and P3 and P3 or D3 and P3 and P4 and P5 and P5 and P5 and P3 and P3 orD1 and P2 and P3 and P4 and P5 and P5 and P7 and P3 and P3 or P4 and P3and P3 and P4 and P5 and P5 and P7 and P3 and P3 and Cm.

In a forty-tive bit adder of the parallel type in which the carries arerippled through from the units position to the last position, a largedelay might be encountered and any order bit must necessarily wait forthe carry in before the sum can be assumed correct. The time savingfeature of the present invention is that simultaneously with the rippleaction through an octal group of three bits in the adder, carries arebeing formed that service bits 4, 7 and l0 so that carry propagation andresolution through each octal bit occur simultaneously. In the presentinvention and considering a nine bit adder with the rst three bits, thesecond three bits and the last three bits operate as parallel ripplecarry adders while carries are being formed simultaneously which will beapplied by the bits 4, 7, and 10. The effect of the overall adder isthat the time is reduced by onethird since the ripple carry occurs inthree-bit units rather than in nine-bit units which operate serially.The original carry in (Cm) encounters only two delays for every ninebits or a total of ten delays for forty-tive bits.

In this application the following conventions will be used: when Xequals l, X equals 0, and when Y equals l, Y equals 0. The booleanexpression (l) will correspond to ground physically, the booleanexpression (0) will correspond to -3 volts physically.

INVERTER In Figure 4 there is shown a functional block diagram of aninverter having an input A and an output The table adjacent to the blockdiagram is the relationship of the signals between the input and output.A suitable circuit arrangement is shown in Figure 5 and cornprises ajunction transistor 200 arranged in a grounded emitter configuration towhich an input signal (0 or 3) is applied at A. A second transistor 202is arranged in an emitter follower configuration and the output sig nalis taken at B. The grounded emitter stage inverts the signal and theemitter follower stage provides a low impedance charge path for the loadcapacity. The inverter circuit is designed to operate at the levels of 0and -3 volts.

The emitter of the transistor 200 is grounded, and the base is connectedthrough a diode 204 to ground; through a K resistor 206 to +10 voltsD.C.; and through an 8.2 K resistor 208 in parallel with the 47micromicrofarad condenser 210 to the input terminal A. A l microfaraddecoupling condenser 212 is connected between -i-lO volt terminal andground. The collector of transistor 200 is connected through a diode 214to -3 volts D.C.; to the base of a transistor 202, and through a 100microhenry coil 216 in series with a 3.3 K resistor 218 to a -10 volts DC. A decoupling condenser 220 is connected between a resistor 218 and a-10 volts D.C. terminal to ground. The collector base junction oftransistor 200 is reverse biased in the usual manner, and the emitter tobase junction is reverse biased to cutoi. Accordingly, when the input isat 0 volts (up), the transistor is cut oit, and the only current iiowingthrough the base collector junction is cutoff current (Ico) and thecollector is clamped at -3 volts through the diode 214. When the point Aof the input is at -3 volts, the voltage across the diode 204 iselfectively across the emitter base junction which forward biases thelatter and saturation collector current ows through the invertertransistor 200 raising its collector to volts.

Diode 222 is connected between the base of transistor 202 and theemitter, the latter being connected to the terminal B, which is theoutput terminal of the inverter. The collector base junction oftransistor 202 is connected to a -3 volts D.C. and connected between thecollector and the output B is a 33 K resistor. A decoupling condenser226 of 1 microfarad is connected between the collector of transistor 202and ground. The purpose of the condenser 210 is to provide a lowirnpedance path to the leading edge of input pulses, to pass transientsto the base, and improve the rise time of the output circuit. Resistor208 determines the base current supplied by the preceding stage andresistor 206 is the temperature compensating resistor which provides thecurrent path for Ico insuring a good cutoff bias to the base. The loadresistor 218 limits the current passed by transistor 200 and supplies aconduction path to the diode 214. Normally with the O volts applied tothe base `of transistor 200 the collector of the latter is clamped at a-3 volts. Upon receiving a voltage shift from 0 to -3 volts at the baseof grounded emitter transistor 200, saturation current flows and thecollector moves from a -3 to slightly above 0 volts. This positive shiftis applied between base and collector of the emitter follower, and theoutput is taken across the emitter and the collector.

NOT AND In Figure 6 there is shown the logical block diagram of a NOTAND circuit used extensively in the following circuits for Anding inputsand presenting this AND function as an output signal that is the inverseof the input. The AND circuit is required to accept at least threeinputs and drive other logical blocks such as and Inverter. From thetruth table adjacent to the functional block diagram there is shown theconditions of the inputs and the resulting condition of the associatedoutput. It will be noted that when both X and Y are up the input isdown. In all other conditions, the output will be up.

With reference to Figure 7, an circuit is shown consisting of invertersconnected in parallel, one inverter for each input. lf any one or all ofthe inverters are conducting because the corresponding inputs are down,the resulting current lflow through the common collector would cause theoutput level to rise to O volts. If all inputs are up, then eachinverter would be cut off and the output level would be down to -3volts. Each of the inverters comprises identical components and only oneinverter will be described. The emitter of the PNP junction transistor230 is connected to ground and the base is returned to ground through adiode 232. The signal is applied at A to the base through an 8.2 Kresistor 234 in parallel with a condenser 236. The base is connected toa +10 volts D.C. through a 100 K resistor 238. A l microfarad decouplingcondenser 240 is connected between -I-lO volts D.C. and resistor 232 toground. The common load consisting of 100 microhenry coil 242 and a 3.3K resistor 244 in series is connected to a -10 volts D.C. A l microhenrycondenser 246 is connected to the -10 volts D.C. line for decouplingpurposes. The output at the collector of the inverters is clamped at a-3 volts through a diode 248 connected between the collectors of thetransistors to -3 volts D.C.

The inverter output is applied to an emitter follower,

and the output of the circuit is taken from D. A diode 253 is connectedbetween the base and the emitter of transistor 250, a 33 K resistor 254is connected between the emitter and the collector, and a l microfaraddecouthe circuit as desired.

OR AND NOT The OR blocks shown in Figure 8 are similar to the A circuitsdescribed previously with additional inverters connected in series inone of the legs. In Figure 9 inverters are connected in series and formthe OR portion of the circuit which is equivalent to one leg of the ANDportion in its effect on the circuit. The transistors 260, 262 in the ORportion are biased so that an up level will cause the correspondingtransistor to be cut otf. Therefore, the entire OR portion will conductonly if all inputs are down permitting the transistors 260 and 262 toconduct. The logic representation shows that the output of the ORportion is applied to acircuit and, accordingly, when any or all inputsto the OR portion are up, and the input to the is up, the output of thecombined circuit is down. The output of the OR portion should not beconsidered as the output of the combined circuit. The truth table shownin Figure 8 is immediately adjacent the functional block diagram.

In Figure 9, the OR Tl circuit comprises the PNP junction transistors260 and 262 connected as inverters and arranged in series to form the ORportion of the circuit. The connections A and B are those inputs to theOR portion which are shown in the block diagram in Figure 8. Thecollector of the transistor 262 is connected in parallel with thecollectors of the transistors 264, 266

and 268 as legs of the AND circuit previously described with respect toFigure 7. The common load is a microhenry coil 270 in series with a 3.3K resistor 272 connected to a -10 volts D.C. The output of the commoncollectors is clamped at a -3 volts D.C. by a diode 274 connectedbetween -3 volts and the common collectors. The voltage shift at thecollector of the transistors as previously mentioned is applied to thebase of the emitter follower transistor 276, the latter being identicalwith the emitter follower described earlier in the line 280 and x or yis applied to line 282 to the circuit 284. The output is taken from line286 and comprises Cin(x|y). Not x and Not y (xy) is applied on line 288to the AND circuit 290. The output, therefore, would be x and y or Cmand x or y which equals Cout in line 292. It should be noted that therst circuit performs the AND function while the second circuit performsthe OR function. It is common practice in transistor logic to use thelogic A as either AND function, OR function or both. The explanationabove applies to carry propagation Within each octal bit.

In Figure 11 the logical blocks are shown for providing a sum at theoutput of the adder. Signals x-and y are applied to the AND circuit 300on lines 302 and 304 respectively. The output is taken from line 306 andconsists of x or y. Signals x and y are applied to AND circuit 310 onlines 312 and 314. The output is taken from line 316 and consists of xor Lines 306 and 316 are the inputs to AND circuit 318, the output ofthe latter being x1 and y1 or x 1 and This output is taken from line 320and is applied to both OR circuit 324 and AND circuit 326. Carry in isapplied on line 328 as an input to both the OR circuit 324 and the ANDcircuit 326, and the output 330 of AND circuit 326 is applied as aninput to the AND circuit 332. The sum is generated on line 334 and isequal to Cm'and x and y or Cin and-f and; or C. and x and.; and C and;and y. The function ofthe rst three ANDs 300, 310 and 318 is to form theif and only if, x and y or and '37, and the "Exclusive OR, x and; or'J-tand y. The if and only if condition is indicated by a positive polarityfrom AND block 318, and the exclusive OR condition is indicated bynegative polarity at the output of block 318. Both of these conditionsare pertinent for the generation of the sum. When AND 318 is used toform the if and only if condition the down Outputs from AND 300 and 310are used.

The following is a truth table for the operation of ANDs 300, 310 and318:

X Y Output Output Output of 300 of 310 of 318 0 down up up 0 l up updown 1 0 up up down 1 l up down up The following is a truth table for ifand only if:

Line 328 Line 320 Line 334 up up up down down up up down down down updown The following is a truth table for Exclusive OR:

Line 328 Line 320 Line 334 (N ot) up up up down down up up down dow-ndown up down The inputs to AND circuit 326 are Cm and the Exclusive OR.The inputs to the OR portion 324 of the OR AND are the Cm and the if andonly if. The output of the OR AND will be the Exclusive OR sum equal toCin and x and y or C and and y or C and x and y or C and is? and y. Inorder to show that the sum is an Exclusive 0R expression consider x andy or 1t-land;d

equal to x and or J-c and y equal to 'l Then the sum may be expressed asthe Exclusive OR of R, and the carry as C and R or C and R.

In Figure 12 there is shown the positive logic blocks which would berequired to accomplish the same thing in a similar manner. Cm is appliedto line 340 to inverter circuit 344 and AND circuit 346 andR is appliedto line 342. to inverter circuit 348 and AND circuit 346. Ac-

cordingly, -'in and R are applied to AND circuit 350. The output at aline 352 is C and R which is then inverted by inverter 354, the outputbeingw and R or C-l-R. The

output of the AND circuit 346 is taken on a line 358 and inverted byinverter 360 and the output at a line 362 is C and-R or 'C-i-R. Thelines '356 and 362 are the inputs to a negative OR circuit 366, and theouttput is taken on a line 368 and inverted in an inverter 370. Theoutput of a line 372 would then be the surn equal to C and R or C and R.It is pointed out that Figures 10 and 11 comprise the adder of Figure 3shown in functional block diagram 2. S0 represents the sum of x and y asshown in the truth table of Figure 3 where S1 represents ST). This isaccomplished by an inversion of S0.

As shown in Figure la, AND blocks 300, 310, 318, 326, 332 and OR circuit324 comprise the logical blocks for generating the sum as shown inFigure 1l and that the ANDs 284 and 290 comprise the carry out as shownin Figure 10. The sum is generated on line 334 as shown in bit positionl. The sum generated on line 334 is applied both to AND circuits 380 and382, and the output of an AND circuit 380 is applied to AND circuit 384.The

AND circuits 380 and 384 form a D.C. latching circuit on the output. Aclock pulse is applied to line 386, and a falling level appears at theoutput of either the sum sum in the adder, this new sum could reach ANDcircuits 382 and 384 before the clock level has been returned to thedown position and an erroneous sum would appear at the outputs. Toprevent the generation of erroneous sums, the outputs of AND circuits382 and 384 are fed back to AND circuits 332 and 380 on surn stops lines388a and 388b, respectively. These feedback paths eiectively latch upthe output of AND circuit 332 and prevent it from changing except whenthe clock is in the up position.

With the clock down, the outputs of AND circuits 382 and 384 are held inthe up position for the next upgoing clock signal and the beginning ofanother cycle.

A group of AND circuits 400, 402, 404, 406 and 408 along with inverters410 and 412 are used to generate the carry into the fourth positionsimultaneously with the application of the pulses to the adder inputs.It will be noted that carry in is applied through line 416 to ANDcircuit 405 and that the carry out of bit position 3 is applied toinverter 410 by way of a line 418. This output at a line 420 isdeveloped by the logic as follows:

Cout=DsiP 3D2-l-P3P aDi-l-P aP 2P 1cm Where Cout S taken from AND 408and Cm is the carry in from line 416. The terms D3|-P3P2D1 are takenfrom the line 418 and applied to the inverter 410, the term P3P2P1Cmbeing generated in ANDs 400, 402, 404 and 405.

From the explanation thus far, it should be evident that the three bitsof positions 4, 5 and 6 of the adder as shown in Figure 1b and the threebits of the positions 7, 8 and 9 of the adder as shown in Figure lcalong with their carry generation circuits for bit positions 7 and 10are substantially the same as those shown in Figure la. Accordingly, itis believed that a detailed explanation of these circuits isunnecessary. In Figure 1b, Cm enters on the line 416, the carry into bitposition 4 enters at the line 420, D3+D2P3+D1P2P3 enters on the line418, and P1P2P3 enters on the line 414. The carry into the seventhposition is generated with the AND circuits 430, 432, 434, 436, 438 and440 with an inverter 442. The output is taken from a line 446 from AND440 and comprises D@+D5P6+DtP6P5+D3P6P5Pr+D2P6P5PtP3nl*D1P6P5P4P3P2-i-PsPaPlrPaPzPiCm output of AND 326 is P4P5P6, whichenters 438 as accesos 'P4P5P6 and is inverted vin inverters 442 and 448..The Aoutput of 438 is"P1P2P3PQP5P6Cmvdue tothe inputs on lines 418 and416 andthe input from` inverter A'442. -The inputs to 440 are the outputof 438aspre'viouslyexplained, the output on the line 448 via an inverter450 iS .D6+D5P6+D4P5- s and the'output of an 452, the latter havinginputsof `D3'}D2`P3|"DiP2P3 and P4P5P6 resulting in the inputs noted.The output from position is provided on a line '466 and isrepresented bythe expression at the bottom of Figure 2. Cout is generated inra-groupof circuits 470, 472, 474, 476, 478, 480, 481, 482, 484 and 486 andinverters 490 and 492. In Ythe manner previously described y 476provides P-,PSPQ which is inverted in inverter 490 and provided on theline 459 as P-lPgPg. The output of v480 is D7PBP9, the output of 481 isDSPs, and the output of an 494 is D9 resulting in an output of 482 ofD9+DP,+D7P8PQ. The output of 478 is P1PaP9(D6+DsPs+D-4P5Ps) which isapplied to A 486. Other inputs to A' 486 are Dg-l-DaPg-l-DqPaPg from theinverter 492 (D3 +D2P3+D1P2P3)P,P5P6P,P,P, from 460 on line 462, andCmP1P2PP4P5P6P7P8P9 from OI! the lille Thus the output-of 486 is ion andit is Spointediout that other transistor circuits or other logicaldevices utilizing other circuit elements may be used in the practice ofthe-invention.

While there have been shown 4and described and pointed out the.fundamental novel features of'the invention as applied to a preferredembodiment, it will be understood that`various omissions andsubstitutions 'and-change in the form and details "of the deviceillustrated and in its operation may be made by those skilled inthe artwithout departing `from the 4spirit of theinvention. It is theintention, therefore, to be limited only as indicated by the scope ofthe following claims:

What is claimed is:

1. In yapparatus for forming the stun of two binary numbers includingAND logical devices, each having input and output means and adapted toprovide a false 'binaryrepresentation at said output means when saidinputnieanslarerexclusively true andotherwise to provide a truebinaryrepresentation, a rst AND logical f'de'vicell and a second N-D.ylogicalfdeviceach'lhavingf a 4`pair of inputs'fn'd-anoutput,fmeans-applying thebinary representation `x Vand--a binaryrepresentation y tosaid vtirstfAND circuit, means`apply-ing-thenegativeof-said binary numbers x and ytosaid secondANDcircuit, a third AND 'circuitlhaving a pair of inputs' and an output,means connecting the'outputof'said 4irst and-second AND'circuits to tbeinput of"said thirdAND` circuit, a fourth AND circuit-having two inputsand an output, an OR'circuit'having"-a'pairofinputs and'an output, meanscoupling *a carry in signal to y'one of `said inputsv offsaidl 0R'circuit and one of saidinputs vto 15V said fourth AND circuit, "meansonnectingtheoutput of said third VAND circuit tothe-other of-saidtinputs to said OR circuit-and the other of said inputs to said fourthAND circuit, -a tifth AND circuitfhaving a pair of inputs and an output,means connecting the outpu-t of saidOR circuit to one of saidinputs ofsaiduffth AND circuit, and means connecting the output of "said 'fourthAND circuitto the other input of said fth AND circuit.

vr2. Inapparatus for forrning the -lsum-tof--two lbinary numbers`including #AND logicaldevices 'responsive to true andfa'lse binarysignals and adapted to provide a false output signal when said inputsare all true signals and otherwise to provideatrueoutput signal, a iirstAND logicaldeviceand a second ANDlogical device, eachhaving :a pair ofinputs land/asingle 'output, means applying a b'inarysignal xv'andabinary signal y to said first AND circuit, means applying'the negativeof said binary numbers x and y'to said second AND circuit, a third ANDcircuit "having a pair `of Ainputs and 'an output, :means connecting the-outputs of 'said rst and second AND c ircuits`to"theinp'ut fsaid thirdAND circuit, a fourth :AND 'circuit yhaving -tvvo'inputs and an output,an OR circuit having a'pair of inputs and an output, means'eoupling a Y"t`arry-i1'1signal'to one of said inputs ofsaid-OR--circuit7and-one-of-said inputs of said fourth AND -'fiircuin *inansfconnectingthe output 1 o'f s'aid lthird -AND c'ircit '-to-ltlie other of having-apair of inputs yandan output, means connecting-the output of said ORcircuit to one of said inputs of said fifth AND circuit, and meansconnecting the output of saidffourth AND circuitlto--the -other input ofsaid-fifth AND circuit.

3. Apparatus-in'accordance With-saidlaim IZWherein additional means areprovided forgenerating Ya-carry out comprising a sixth- AND-crcuithavinga' pair' of inputs 'and an output, means connectingthe second :ANDcircuit output to'one 4of the linputs of Asaid 'sixth AND circuit, meansconnecting the carry in signal Yto the other of1said inputs of saidsixth AND circuit,a seventh to the other -of said inputs to said seventhAND circuit. 4. Apparatus for generating la carry from an-octai adder toa fourth order of an adder including AND circuits responsive to true andfalse binary signals and adapted to provide a false output`signal'whenthe inputs are alltruesignals and otherwise 'providea trueoutput signal comprising .fmeans providing signals indicative -ofnegative of x2 and y2 to said inputs, a second AND circuit, having apair of inputs and an output, means providing the negative of x3 and yato said inputs of said second AND circuit, a third AND circuit havingfour inputs and a pair of outputs, means coupling signals x1 and x2 totwo of said inputs, means coupling the outputs of said rst and secondAND circuits to the other of two inputs of said third AND circuit, afourth AND circuit having three inputs and an output, means coupling oneof the outputs of said third D circuit to one of the inputs of saidfourth m circuit, means providing x2 and y2 to the other two inputs ofsaid fourth .AW circuit, a iifth-ND circuit having three inputs and anoutput, a sixth 'XN-D circuit having two inputs and an output, meanscoupling x3 and y3 to said sixthmcircuit, said output of said sixth AN-D circuit being connected to one of the inputs of said fifth mcircuit, means connecting the other of said outputs of said third micircuit to another of said inputs of said iifth m circuit, meansconnecting the output of said fourth -D circuit to the input of saidfifth AND circuit, a seventh AND circuit having a pair of inputs and anoutput, means applying the negative of x1 and y1 to said inputs of saidseventh AND circuit, an eighth AND circuit having two inputs and anoutput, means applying the negative of x2 and y2 to said inputs of saideighth AND circuit, a ninth AND circuit having a pair of inputs and anoutput, means applying the negative of x3 and ya to said inputs of saidninth AND circuit, a tenth AND circuit having four inputs and an output,means connecting the outputs of said seventh, eighth and ninth ANDcircuits to a respective one of said inputs of said tenth AND circuit,means connecting the carry in to the other of said inputs of Said tenthAND circuit, an inverter having an input and an output, means connectingthe output of said fth AND circuit to the input of said invertercircuit, an eleventh AND circuit having two inputs and an output, meansconnecting the output of said tenth AND circuit to one of the inputs ofsaid eleventh AND circuit, and means connecting the output of saidinverter circuit to the other of said inputs of said eleventh ANDcircuit.

5. In an adder for the parallel addition of binary numbers of which -theserial carry operation is broken into groups and the carries betweengroups are generated simultaneously with the addition of said binarynumbers and AND logical devices are employed which are responsive totrue and false binary signals so that a false output is provided whenthe inputs are all true signals and otherwise a true output signal isprovided, a group of adders comprising at least one adder having a firstAND logical device and a second AND logical device,

each having a pair of inputs and an output, means applying a binaryrepresentation x and a binary representation y to said iirst ANDcircuit, means applying the negative of said binary numbers x and y tosaid second AND circuit, a third AND circuit having a pair of inputs andan output, means connecting the outputs of said first and second ANDcircuits to the input of said third AND circuit, a fourth AND circuithaving two inputs and an output, an OR circuit having a pair of inputsand anr output, means coupling a carry in signal to one of said inputsof said OR circuit and one of said inputs of said fourth AND circuit,means connecting the output of said third AND circuit to the other ofsaid inputs to said OR circuit, and the other of said inputs to saidfourth AND circuit, a fth AND circuit having a pair of inputs and anoutput, means connecting the output of said OR circuit to one of saidinputs of said lifth AND circuit, means connecting the output of saidfourth AND circuit to the addition of said binary numbers and ANDlogical devices are employed which are responsive to true and falsebinary signals so that a false output is provided when the inputs areall true signals and otherwise a true output signal is provided, anadder for each order of said groups comprising at least one adder havinga rst AND logical device and a second AND logical device, each having apair of inputs and an output, means applying a binary representation xand a binary representation y to said rst AND circuit, means applyingthe negative of said binary numbers x and y to said second AND circuit,a

third AND circuit having a pair of inputs and an output, meansconnecting the output of said rst and second AND circuits to the inputsof said third AND circuit, a

fourth AND circuit having two inputs and an output, an OR circuit havinga pair of inputs and an output, means coupling a carry in signal to oneof said inputs of said OR circuit and one of said inputs of said fourthAND circuit, means connecting the output of said third AND circuit tothe other of said inputs of said OR circuit and the other of said inputsto said fourth AND circuit, a

fifth AND circuit having a pair of inputs and an output, meansconnecting the output of said OR circuit to one of said inputs of saidfth AND circuit, means connecting the output of said fourth AND circuitto the input of said fifth AND circuit, and carry generation means forpropagating a carry out of at least one of said groups simultaneouslywith the parallel addition of said binary numbers comprising a sixth ANDcircuit having a pair of inputs and an output, means applying thenegative of x2 and y2 to said inputs, a seventh AND circuit having apair of inputs and an output, means providing the neg ative of x3 and yato said inputs of said seventh AND circuit, an eighth AND circuit havingfour inputs and a pair of outputs, means coupling signals x1 and x2 totwo of said inputs, means coupling the output of said sixth and seventhAND circuits to the other of two inputs of said eighth AND circuit, aninth AND circuit having three inputs and an output, means coupling oneof the outputs of said eighthl) circuit to one of the inputs of saidninth im circuit, means providing x2 and y2 to the other two inputs ofsaid ninth-AN-D circuit, a tenth m circuit having three inputs and anoutput, an eleventh 'Ncircuit having two inputs and an output, meanscoupling x3 and y3 to said eleventh m circuit, said output of saideleventh m circuit being connected to one 13 of the inputs of said tenthA N- lI-- circuit, means connecting the other of said outputs of saideighth 'AN-D circuit to another of said inputs of said tenth '-D'circuit, means connecting the output of said ninthm circuit to the inputof said tenth AND circuit, a twelfth AND circuit having a pair of inputsand an output, means applying the negative of x1 and y1 to said inputsof said seventh AND circuit, a thirteenth AND circuit having two inputsand an output, means applying the negatives of x2 and y2 to said inputsof said thirteenth AND circuit, a fourteenth AND circuit having a pairof inputs and an output, means applying the negative -of x3 and ya tosaid inputs of said fourteenth AND circuit, a fifteenth AND circuithaving four inputs and an output, means connecting the outputs of saidtwelfth, thirteenth and fourteenth m circuits to the respective one ofsaid inputs of said fifteenth m circuit, means connecting the carry into the other of said inputs of said fifteenth m circuit, an inverterhaving an input and an output, means connecting the output of said tenthAND circuit to the input of said inverter circuit, a sixteenth ANDcircuit having two inputs and an output, means connecting the output ofsaid fteenth AND circuit to one of the inputs of said sixteenth ANDcircuit, and means connecting the output of said inverter circuit to theother of said inputs of said sixteenth AND circuit.

7. In an adder for the parallel addition of binary numbers in which theserial carry operation is broken up into octal groups of three adderorders and carries between said groups are generated simultaneously withthe addition of said binary numbers and AND circuits are employed whichare responsive -to true and false binary signals so that a false outputis provided when lthe inputs are all true signals and otherwise a trueoutput signal is provided, an adder for each order of said groups and atleast one carry generation circuit for an octal group comprising meansproviding signals indicative of binary bits from a number x and a numbery and a carry in, a irst AND circuit having a pair of inputs and anoutput, means applying the negative of x2 and y2 to said inputs, asecond mi circuit, means providing the negative of x3 and ys to saidinputs, a third AND circuit having four inputs and a pair of outputs,means coupling signals x1 and x2 to two of said inputs, means couplingthe output of said first and second ED cir cuit to the other of twoinputs of said third AND circuit, a fourth AND circuit having threeinputs, means coupling one of the outputs of said third AND circuit toone of the inputs of said fourth AND circuit, means applying x2 and y2to the other two inputs of said fourth AND circuit, a iifth AND circuithaving three inputs and an output, a sixth AND circuit having a pair ofinputs and an output, means coupling x3 and ya to said sixth ANDcircuit, said output of said sixth AND circuit being connected to theinput of said fifth AND circuit, means connecting the other two of saidoutputs of said third AND circuit to another of said inputs of saidfifth AND circuit, means connecting the output of said fourth ANDcircuit to the input of said fifth AND circuit, a seventh AND circuithaving a pair of inputs and an output, means applying the negative of x1and y1 to said inputs of said seventh AND circuit, an eighth AND circuithaving two inputs and an output, means applying the negative of x2 andy2 to said inputs of said eighth AND circuit, a ninth AND circuit havinga pair of inputs and an output, means applying the negative of x3 and yato said inputs of said ninth AND circuit, a tenth AND circuit havingfour inputs and an output, means connecting the output of said seventh,eighth and ninth AND circuits to a respective one of said inputs of saidtenth AND circuit, means connecting the carry in signal to the other ofsaid inputs of said tenth AND circuit, an inverter having an input andan output, means connecting the output of said iifth AND circuit to theinput of said inverter circuit, an eleventh AND circuit having twoinputs and an output, means connecting the output of said tenth ANDcircuit to one of the inputs of said eleventh AND circuit, and meansconnecting the output of said inverter circuit to the other of saidinputs of said eleventh AND circuit.

8. In an adder for the parallel addition of binary numbers having groupsof orders in which the carry operation is serial within groups and ANDlogic devices are employed which are responsive to true and false binarysignals so that a false output is provided when the inputs are all truesignals, an adder for each order of said groups, means coupling thecarry in signal to said adder, means applying binary numbers in paralledto said adder orders, carry generating means comprising negative logictransistor circuits for performing AND functions and OR functions togenerate carries between said groups simultaneously with the addition ofsaid numbers, means applying said binary numbers to said carrygenerating means, and means applying said carry in signal to said carrygenerating means.

References Cited in the le of this patent UNITED STATES PATENTS Jacobset al. Oct. 4, 1955 Weinberger et al. Mar. 24, 1959 OTHER REFERENCES

